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rev: 1.02 11/2002 1/32 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. nobl is a trademark of cypress semiconducto r corp.. ntram is a trademark of samsung el ectronics co.. zbt is a trademark of inte grated device technology, inc. preliminary gs842z18/36ab-180/166/150/100 4mb pipelined and flow through synchronous nbt srams 180 mhz?100 mhz 3.3 v v dd 2.5 v and 3.3 v v ddq 119-bump bga commercial temp industrial temp features ? 256k x 18 and 128k x 36 configurations ? user configurable pipeline and flow through mode ? nbt (no bus turn around) functionality allows zero wait read-write-read bus utilization ? fully pin compatible with both pipelined and flow through ntram?, nobl? and zbt? srams ? pin-compatible with 2m, 8m, and 16m devices ? 3.3 v +10%/?10% core power supply ? 2.5 v or 3.3 v i/o supply ? lbo pin for linear or interleave burst mode ? byte write operation (9-bit bytes) ? 3 chip enable signals for easy depth expansion ? clock control, registered address, data, and control ? zz pin for automatic power-down ? jedec-standard 11 9-bump bga package functional description the gs842z18/36ab is a 4mbit synchronous static sram. gsi's nbt srams, like zbt, ntram, nobl or other pipelined read/double late write or flow through read/single late write srams, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles. because it is a synchronous devi ce, address, data inputs, and read/ write control inputs are ca ptured on the rising edge of the input clock. burst order control (lbo ) must be tied to a power rail for proper operation. asynchronous inputs include the sleep mode enable (zz) and outp ut enable. output enable can be used to override the synchronous control of the output drivers and turn the ram's output drivers off at any time. write cycles are internally self- timed and initiated by the rising edge of the clock input. this feature eliminates complex off- chip write pulse generation required by asynchronous srams and simplifies input signal timing. the gs842z18/36at may be configured by the user to operate in pipeline or flow through mode. operating as a pipelined synchronous device, in addition to the rising-edge- triggered registers that capture input signals, the device incorporates a rising-edge-triggered output register. for read cycles, pipelined sram output data is temporarily stored by the edge triggered output regi ster during the access cycle and then released to the output driv ers at the next rising edge of clock. the gs842z18/36at is implemented with gsi's high performance cmos technology and is available in a jedec- standard 119-bump bga package. ?180 ?166 ?150 ?100 pipeline 3-1-1-1 tcycle t kq i dd 5.5 ns 3.2 ns 335 ma 6.0 ns 3.5 ns 310 ma 6.6 ns 3.8 ns 280 ma 10 ns 4.5 ns 190 ma flow through 2-1-1-1 t kq tcycle i dd 8 ns 9.1 ns 210 ma 8.5 ns 10 ns 190 ma 10 ns 12 ns 165 ma 12 ns 15 ns 135 ma abcdef rwrwrw q a d b q c d d q e q a d b q c d d q e clock address read/write flow through data i/o pipelined data i/o flow through and pipelined nbt sram back-to-back read/write cycles
rev: 1.02 11/2002 2/32 ? 2001, giga semiconductor, inc. specifications cited are subject to change without noti ce. for latest documentation see http://www.gsitechnology.com preliminary gs842z18/36ab-180/166/150/100 gs842z18a pad out 119 bump bga ? top view 1234567 a v ddq a 6 a 7 nc a 8 a 9 v ddq b nc e 2 a 4 adv a 15 e 3 nc c nc a 5 a 3 v dd a 14 a 16 nc d dq b1 nc v ss zq v ss dq a9 nc e nc dq b2 v ss e 1 v ss nc dq a8 f v ddq nc v ss g v ss dq a7 v ddq g nc dq b3 b b nc nc nc dq a6 h dq b4 n c v ss w v ss dq a5 nc j v ddq v dd nc v dd nc v dd v ddq k nc dq b5 v ss ck v ss nc dq a4 l dq b6 nc nc nc b a dq a3 nc m v ddq dq b7 v ss cke v ss nc v ddq n dq b8 nc v ss a 1 v ss dq a2 nc p nc dq b9 v ss a 0 v ss nc dq a1 r nc a 2 lbo v dd ft a 13 nc t nc a 10 a 11 nc a 12 a 17 zz u v ddq tms tdi tck tdo nc v ddq
rev: 1.02 11/2002 3/32 ? 2001, giga semiconductor, inc. specifications cited are subject to change without noti ce. for latest documentation see http://www.gsitechnology.com preliminary gs842z18/36ab-180/166/150/100 gs842z36a pad out 119 bump bga ? top view 1234567 a v ddq a 6 a 7 nc a 8 a 9 v ddq b nc e 2 a 4 adv a 15 e 3 nc c nc a 5 a 3 v dd a 14 a 16 nc d dq c4 dq c9 v ss zq v ss dq b9 dq b4 e dq c3 dq c8 v ss e 1 v ss dq b8 dq b3 f v ddq dq c7 v ss g v ss dq b7 v ddq g dq c2 dq c6 b c nc b b dq b6 dq b2 h dq c1 dq c5 v ss w v ss dq b5 dq b1 j v ddq v dd nc v dd nc v dd v ddq k dq d1 dq d5 v ss ck v ss dq a5 dq a1 l dq d2 dq d6 b d nc b a dq a6 dq a2 m v ddq dq d7 v ss cke v ss dq a7 v ddq n dq d3 dq d8 v ss a 1 v ss dq a8 dq a3 p dq d4 dq d9 v ss a 0 v ss dq a9 dq a4 r nc a 2 lbo v dd ft a 13 nc t nc nc a 10 a 11 a 12 nc zz u v ddq tms tdi tck tdo nc v ddq
rev: 1.02 11/2002 4/32 ? 2001, giga semiconductor, inc. specifications cited are subject to change without noti ce. for latest documentation see http://www.gsitechnology.com preliminary gs842z18/36ab-180/166/150/100 gs842z18/36a pin description symbol type description a 0 , a 1 i address field lsbs and address counter preset inputs an i address inputs dq a1 ? dq a9 dq b 1 ? dq b 9 dq c1 ? dq c 9 dq d 1 ? dq d 9 i/o data input and output pins b a , b b , b c , b d i byte write enable for dq a , dq b , dq c , dq a i/os; active low ( x36 version) ck i clock input signal; active high cke i clock input buffer enable; active low w i write enable. writes all enabled bytes; active low e 1 , e 3 i chip enable; active low e 2 i chip enable; active high g i output enable; active low adv i burst address counter advance enable; active high zz i sleep mode control; active high ft i flow through or pipeline mode; active low lbo i linear burst order mode; active low zq i flxdrive output impedance control (low = low impedance [high drive], high = high impedance [low drive]) nc ? no connect tms i scan test mode select tdi i scan test data in tdo o scan test data out tck i scan test clock v dd i core power supply v ss i i/o and core ground v ddq i output driver power supply ck i clock input signal; active high
rev: 1.02 11/2002 5/32 ? 2001, giga semiconductor, inc. specifications cited are subject to change without noti ce. for latest documentation see http://www.gsitechnology.com preliminary gs842z18/36ab-180/166/150/100 functional details clocking deassertion of the clock enable (cke ) input blocks the clock input fr om reaching the ram's internal circuits. it may be used to suspend ram operations. failure to observ e clock enable set-up or hold requirem ents will result in erratic operation. pipelined mode read and write operations all inputs (with the exception of output enab le, linear burst order and sleep) are synchr onized to rising clock edges. single c ycle read and write operati ons must be initiated with the advance/load pin (adv) held low, in order to load the new address. device activation is accomplished by asserting al l three of the chip enable inputs (e 1 , e 2, and e 3 ). deassertion of any one of the enable inputs will deactivate the device. read operation is initiated when the following conditions are satisfied at the rising edge of clock: cke is asserted low, all three chip enables (e1 , e2, and e3 ) are active, the write enable input signal w is deasserted high, and adv is asserted low. the address presented to the address inputs is latched in to address register and presented to the memory core and control logic. the contr ol logic determines that a read access is in progress and allows th e requested data to propagate to the input of the output regist er. at the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins. write operation occurs when the ram is selected, cke is active a nd the write input is sampled low at the rising edge of clock. the byte write enable inputs (b a , b b , b c, and b d ) determine which bytes will be written. all or none may be activated. a write cycle with no byte write inputs active is a no-op cycle. the pipelined nbt sram provides double late write functionality, matching th e write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). at the first r ising edge of clock, enable, write, byte write(s) , and address are registered. the data in a ssociated with that address is required a t the third rising edge of clock. flow through mode read and write operations operation of the ram in flow through mode is very similar to operations in pipeline mode. activation of a read cycle and the us e of the burst address counter is identical. in flow through mode the device may begin driving out new data immediately after new address are clocked into the ram, rather than holding new data until the following (second) clock edge. therefore, in flow through mode the read pipeline is one cycle shorter than in pipeline mode. write operations are initiated in the same way as well, but diff er in that the write pipeline is one cycle shorter as well, pre serving the ability to turn the bus from reads to writes without inserting any dead cycles. while the pipelined nbt rams implement a double late write protocol, in flow through mode a single late wr ite protocol mode is observed. therefore, in flow through mode , address and control are registered on the first rising edge of cl ock and data in is required at the data input pins at the seco nd rising edge of clock. function w b a b b b c b d read h x x x x write byte ?a? l l h h h write byte ?b? l h l h h write byte ?c? l h h l h write byte ?d? l h h h l write all bytes l l l l l write abort/nop l h h h h
rev: 1.02 11/2002 6/32 ? 2001, giga semiconductor, inc. specifications cited are subject to change without noti ce. for latest documentation see http://www.gsitechnology.com preliminary gs842z18/36ab-180/166/150/100 synchronous truth table operation type address e 1 e 2 e 3 zz adv w bx g cke ck dq notes deselect cycle, power down d none h x x l l x x x l l-h high-z deselect cycle, power down d none x x h l l x x x l l-h high-z deselect cycle, power down d none x l x l l x x x l l-h high-z deselect cycle, continue d none x x x l h x x x l l-h high-z 1 read cycle, begin burst r external l h l l l h x l l l-h q read cycle, continue burst b next x x x l h x x l l l-h q 1,10 nop/read, begin burst r external l h l l l h x h l l-h high-z 2 dummy read, continue burst b next x x x l h x x h l l-h high-z 1,2,10 write cycle, begin burst w external l h l l l l l x l l-h d 3 write cycle, continue burst b next x x x l h x l x l l-h d 1,3,10 nop/write abort, begin burst w none l h l l l l h x l l-h high-z 2,3 write abort, continue burst b next x x x l h x h x l l-h high-z 1,2,3,10 clock edge ignore, stall current x x x l x x x x h l-h - 4 sleep mode none x x x h x x x x x x high-z notes: 1. continue burst cycles, whether read or write, use the same control inputs; a deselect continue cycle can only be entered into if a deselect cycle is executed first 2. dummy read and write abort can be consider ed nops because the sram performs no opera tion. a write abort occurs when the w pin is sampled low, but no byte write pins are active, so no write operation is performed. 3. g can be wired low to minimize the number of control signals provi ded to the sram. output drivers will automatically turn off du ring write cycles. 4. if cke high occurs during a pipelined read cycle, the dq bus will remain active (low z). if cke high occurs during a wr ite cycle, the bus will remain in high z. 5. x = don?t care; h = logic high; l = logic low; bx = high = all byte write signals are high; bx = low = one or more byte/write signals are low 6. all inputs, except g and zz, must meet setup and hold times of rising clock edge. 7. wait states can be inserted by setting cke high. 8. this device contains circuitry that ensur es all outputs are in high z during power-up. 9. a 2-bit burst counter is incorporated. 10. the address counter is incriminat ed for all burst continue cycles.
rev: 1.02 11/2002 7/32 ? 2001, giga semiconductor, inc. specifications cited are subject to change without noti ce. for latest documentation see http://www.gsitechnology.com preliminary gs842z18/36ab-180/166/150/100 deselect new read new write burst read burst write w r b r b w d d b b w r d b w r d d pipelined and flow through read-w rite control state diagram current state (n) next state (n+1) transition ? input command code key notes 1. the hold command (cke low) is not shown because it prevents any state change. 2. w, r, b, and d represent input command codes as indicated in t he synchronous truth table. clock (ck) command current state next state ? n n+1 n+2 n+3 ??? current state and next state definition for pipelined and flow through read /write control state diagram w r
rev: 1.02 11/2002 8/32 ? 2001, giga semiconductor, inc. specifications cited are subject to change without noti ce. for latest documentation see http://www.gsitechnology.com preliminary gs842z18/36ab-180/166/150/100 intermediate intermediate intermediate intermediate intermediate intermediate high z (data in) data out (q valid) high z b w b r b d r w r w d d pipeline mode data i/o state diagram current state (n) next state (n+2) transition ? input command code key transition intermediate state (n+1) notes 1. the hold command (cke low) is not shown because it prevents any state change. 2. w, r, b, and d represent input command codes as indicated in the truth tables. clock (ck) command current state intermediate ? n n+1 n+2 n+3 ??? current state and next state definition for pipeline mode data i/o state diagram next state state
rev: 1.02 11/2002 9/32 ? 2001, giga semiconductor, inc. specifications cited are subject to change without noti ce. for latest documentation see http://www.gsitechnology.com preliminary gs842z18/36ab-180/166/150/100 high z (data in) data out (q valid) high z b w b r b d r w r w d d current state (n) next state (n+1) transition ? input command code key notes 1. the hold command (cke low) is not shown because it prevents any state change. 2. w, r, b, and d represent input command codes as indicated in the truth tables. flow through mode da ta i/o state diagram clock (ck) command current state next state ? n n+1 n+2 n+3 ??? current state and next state definition for: pipelined and flow through read write control state diagram
rev: 1.02 11/2002 10/32 ? 2001, giga semiconductor, inc. specifications cited are subject to change without noti ce. for latest documentation see http://www.gsitechnology.com preliminary gs842z18/36ab-180/166/150/100 burst cycles although nbt rams are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from read to write, multiple back-t o-back reads or writes may al so be performed. nbt srams provide an on-chip burst address generator that can be utilized, if desired, to further simplify burst read or write implementatio ns. the adv control pin, when driven high, commands the sram to advance the internal address counter and use the c ounter generated address to read or write the sram. the starting address for the first cy cle in a burst cycle series is loaded in to the sram by driving the adv pin low, into load mode. burst order the burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been accessed. the burst sequence is determined by the state of the lin ear burst order pin (lbo ). when this pin is low, a linear burst sequence is selected. when the ram is installed with the lbo pi n tied high, interleaved burst sequence is selected. see the tab les below for details. flxdrive? the zq pin allows selection between nbt ram nominal drive strength (zq low) for multi-drop bus applications and low drive strength (zq floating or high) point-to-point applications . see the output driver char acteristics chart for details. note: there is a are pull-up devices on the lbo , zq, and ft pins and a pull down device on the pe and zz pins, so those input pins can be unconnected and the chip will operate in the defaul t states as specified in the above table. burst counter sequences bpr 1999.05.18 mode pin functions mode name pin name state function burst order control lbo l linear burst h or nc interleaved burst output register control ft l flow through h or nc pipeline power down control zz l or nc active h standby, i dd = i sb flxdrive output impedance control zq l high drive (low impedance) h or nc low drive (high impedance) linear burst sequence note: the burst counter wraps to initial state on the 5th clock. i nterleaved burst sequence note: the burst counter wraps to initial state on the 5th clock. a[1:0] a[1:0] a[1:0] a[1:0] 1st address 00 01 10 11 2nd address 01 10 11 00 3rd address 10 11 00 01 4th address 11 00 01 10 a[1:0] a[1:0] a[1:0] a[1:0] 1st address 00 01 10 11 2nd address 01 00 11 10 3rd address 10 11 00 01 4th address 11 10 01 00
rev: 1.02 11/2002 11/32 ? 2001, giga semiconductor, inc. specifications cited are subject to change without noti ce. for latest documentation see http://www.gsitechnology.com preliminary gs842z18/36ab-180/166/150/100 sleep mode during normal operation, zz must be pulled low, either by the us er or by its internal pull-down resistor. when zz is pulled hig h, the sram will enter a power sleep mode after 2 cycles. at this time, internal stat e of the sram is preserved. when zz returns t o low, the sram operates normally af ter 2 cycles of wake up time. sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to i sb 2. the duration of sleep mode is dictated by the length of tim e the zz is in a high state. after ente ring sleep mode, all inputs except zz become disabled and all outputs go to high-z the zz pin is an async hronous, active high input that cau ses the device to enter sleep mo de. when the zz pin is driven high, i sb 2 is guaranteed after the time tzzi is met. because zz is an asynchronous input, pending operations or operations in progress may not be properly completed if zz is asserted. therefore, sleep mode must not be initiat ed until valid pending operations are completed. similarly, when exit ing sleep mode during tzzr, only a deselect or read commands may be applied while the sram is recovering from sleep mode. sleep mode timing diagram designing for compatibility the gsi nbt srams offer users a configurable selection between flow through mode and pipeline mode via the ft signal found on bump r5. not all vendors offer this option, however, most mark bump r5 as v dd or v ddq on pipelined parts and v ss on flow through parts. gsi nbt srams are fully compatible with these sockets. ck zz tzzr tzzh tzzs ~ ~ ~ ~ sleep ~ ~ ~ ~ ~ ~
rev: 1.02 11/2002 12/32 ? 2001, giga semiconductor, inc. specifications cited are subject to change without noti ce. for latest documentation see http://www.gsitechnology.com preliminary gs842z18/36ab-180/166/150/100 note: permanent damage to the device may occur if the absolute maximum ratings are exceeded. operation should be restricted to recomm ended operating conditions. exposure to conditions exceeding the absolute maximum ratings, for an extended period of time, may affect reliability of this component. notes: 1. unless otherwise noted, all performance specificatio ns quoted are evaluated for worst case at both 2.75 v v ddq 2.375 v (i.e., 2.5 v i/o) and 3.6 v v ddq 3.135 v (i.e., 3.3 v i/o), and quoted at whichever condition is worst case. 2. this device features input buffers compat ible with both 3.3 v and 2.5 v i/o drivers. 3. most speed grades and configurations of this device are offer ed in both commercial and industrial temperature ranges. the pa rt number of industrial temperature range versions end t he character ?i?. unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 4. input under/overshoot voltage must be ?2 v > vi < v dd +2 v with a pulse width not to exceed 20% tkc. absolute maximum ratings (all voltages reference to v ss ) symbol description value unit v dd voltage on v dd pins ?0.5 to 4.6 v v ddq voltage in v ddq pins ?0.5 to v dd v v ck voltage on clock input pin ?0.5 to 6 v v i/o voltage on i/o pins ?0.5 to v ddq +0.5 ( 4.6 v max.) v v in voltage on other input pins ?0.5 to v dd +0.5 ( 4.6 v max.) v i in input current on any pin +/?20 ma i out output current on any i/o pin +/?20 ma p d package power dissipation 1.5 w t stg storage temperature ?55 to 125 o c t bias temperature under bias ?55 to 125 o c recommended oper ating conditions parameter symbol min. typ. max. unit notes supply voltage v dd 3.135 3.3 3.6 v i/o supply voltage v ddq 2.375 2.5 v dd v1 input high voltage v ih 1.7 ? v dd +0.3 v2 input low voltage v il ?0.3 ? 0.8 v 2 ambient temperature (com mercial range versions) t a 02570 c3 ambient temperature (industrial range versions) t a ?40 25 85 c3
rev: 1.02 11/2002 13/32 ? 2001, giga semiconductor, inc. specifications cited are subject to change without noti ce. for latest documentation see http://www.gsitechnology.com preliminary gs842z18/36ab-180/166/150/100 note: these parameters are sample tested. notes: 1. junction temperature is a function of sr am power dissipation, package thermal resist ance, mounting board temperature, ambient . temperature air flow, board density, and pcb thermal resistance. 2. scmi g-38-87 3. average thermal resistance between die and top surface, mil spec-883, method 1012.1 capacitance (t a = 25 o c, f = 1 mh z , v dd = 3.3 v) parameter symbol test conditions typ. max. unit input capacitance c in v in = 0 v 45pf input/output capacitance c i/o v out = 0 v 67pf package thermal characteristics rating layer board symbol max unit notes junction to ambient (at 200 lfm) single r ja 40 c/w 1,2 junction to ambient (at 200 lfm) four r ja 24 c/w 1,2 junction to case (top) ? r jc 9 c/w 3 20% tkc v ss ? 2.0 v 50% v ss v ih undershoot measurement and timing overshoot measurement and timing 20% tkc v dd + 2.0 v 50% v dd v il
rev: 1.02 11/2002 14/32 ? 2001, giga semiconductor, inc. specifications cited are subject to change without noti ce. for latest documentation see http://www.gsitechnology.com preliminary gs842z18/36ab-180/166/150/100 notes: 1. include scope and jig capacitance. 2. test conditions as specified wi th output loading as shown in fig. 1 unless otherwise noted. 3. output load 2 for t lz , t hz , t olz and t ohz 4. device is deselected as defined by the truth table. ac test conditions parameter conditions input high level 2.3 v input low level 0.2 v input slew rate 1 v/ns input reference level 1.25 v output reference level 1.25 v output load fig. 1& 2 dc electrical characteristics parameter symbol test conditions min max input leakage current (except mode pins) i il v in = 0 to v dd ?1 ua 1 ua zz input current i inzz v dd v in v ih 0 v v in v ih ?1 ua ?1 ua 1 ua 300 ua mode pin input current i inm v dd v in v il 0 v v in v il ?300 ua ?1 ua 1 ua 1 ua output leakage current i ol output disable, v out = 0 to v dd ?1 ua 1 ua output high voltage v oh i oh = ?8 ma, v ddq = 2.375 v 1.7 v ? output high voltage v oh i oh = ?8 ma, v ddq = 3.135 v 2.4 v ? output low voltage v ol i ol = 8 ma ? 0.4 v dq vt = 1.25 v 50 ? 30pf * dq 2.5 v output load 1 output load 2 225 ? 225 ? 5pf * * distributed test jig capacitance
rev: 1.02 11/2002 15/32 ? 2001, giga semiconductor, inc. specifications cited are subject to change without noti ce. for latest documentation see http://www.gsitechnology.com preliminary gs842z18/36ab-180/166/150/100 operating currents parameter test conditions symbol - 180 - 166 - 150 - 100 unit 0 to 70c ?40 to 85c 0 to 70c ?40 to 85c 0 to 70c ?40 to 85c 0 to 70c ?40 to 85c operating current device selected; all other inputs v ih o r v il output open i dd pipeline 335 345 310 320 280 290 190 200 ma i dd flow-thru 210 220 190 200 165 175 135 145 ma standby current zz v dd ? 0.2 v i sb pipeline 20 30 20 30 20 30 20 30 ma i sb flow-thru 20 30 20 30 20 30 20 30 ma deselect current device deselected; all other inputs v ih or v il i dd pipeline 55 65 50 60 50 60 40 50 ma i dd flow-thru 40 50 40 50 35 45 35 45 ma
rev: 1.02 11/2002 16/32 ? 2001, giga semiconductor, inc. specifications cited are subject to change without noti ce. for latest documentation see http://www.gsitechnology.com preliminary gs842z18/36ab-180/166/150/100 ac electrical characteristics notes: 1. these parameters are sampled and are not 100% tested 2. zz is an asynchronous signal. however, in order to be recognized on any given clock cycl e, zz must meet the specified setup a nd hold times as specified above. parameter symbol -180 -166 -150 -100 unit min max min max min max min max pipeline clock cycle time tkc 5.5 ? 6.0 ? 6.7 ? 10 ? ns clock to output valid tkq ? 3.2 ? 3.5 ? 3.8 ? 4.5 ns clock to output invalid tkqx 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns clock to output in low-z tlz 1 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns flow through clock cycle time tkc 9.1 ? 10.0 ? 12.0 ? 15.0 ? ns clock to output valid tkq ? 8.0 ? 8.5 ? 10.0 ? 12.0 ns clock to output invalid tkqx 3.0 ? 3.0 ? 3.0 ? 3.0 ? ns clock to output in low-z tlz 1 3.0 ? 3.0 ? 3.0 ? 3.0 ? ns clock high time tkh 1.3 ? 1.3 ? 1.3 ? 1.3 ? ns clock low time tkl 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns clock to output in high-z thz 1 1.5 3.2 1.5 3.5 1.5 3.8 1.5 5 ns g to output valid toe ? 3.2 ? 3.5 ? 3.8 ? 5 ns g to output in low-z tolz 1 0 ? 0 ? 0?0?ns g to output in high-z tohz 1 ? 3.2 ? 3.5 ? 3.8 ? 5 ns setup time ts 1.5 ? 1.5 ? 1.5 ? 2.0 ? ns hold time th 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns zz setup time tzzs 2 5 ? 5 ? 5?5?ns zz hold time tzzh 2 1 ? 1 ? 1?1?ns zz recovery tzzr 20 ? 20 ? 20 ? 20 ? ns
rev: 1.02 11/2002 17/32 ? 2001, giga semiconductor, inc. specifications cited are subject to change without noti ce. for latest documentation see http://www.gsitechnology.com preliminary gs842z18/36ab-180/166/150/100 pipeline mode read/write cycle timing *note: e = high (false) if e 1 = 1 or e 2 = 0 or e 3 = 1 th ts th ck cke e * adv tkh w tkl tkc ts b n a 0 ?an a1 th ts a2 a3 d(a1) d(a2) q(a3) q q(a6) th ts d d(a5) tlz tkq tkqx tohz tolz tkqx thz toe g 12 3 456 7 8 910 command write d(a1) write d(a2) burst write d(a2+1) read q(a3) read q(a4) burst read q(a4+1) write d(a5) read q(a6) write d(a7) deselect don?t care undefined dq a ?dq d th ts th ts th ts a4 a5 a6 a7 q(a4) (a4+1) (a2+1)
rev: 1.02 11/2002 18/32 ? 2001, giga semiconductor, inc. specifications cited are subject to change without noti ce. for latest documentation see http://www.gsitechnology.com preliminary gs842z18/36ab-180/166/150/100 pipeline mode no-op, stall and deselect timing *note: e = high (false) if e 1 = 1 or e 2 = 0 or e 3 = 1 ck cke e * adv w bn a 0 ?an a1 a5 d(a1) q(a2) q(a3) q(a5) dq 1 2 3 4 56 7 8 9 10 command write d(a1) read q(a2) stall read q(a3) write d(a4) stall nop read q(a5) continue don?t care undefined d(a4) thz tkqx deselect deselect th ts a2 a3 a4 th ts th ts th ts
rev: 1.02 11/2002 19/32 ? 2001, giga semiconductor, inc. specifications cited are subject to change without noti ce. for latest documentation see http://www.gsitechnology.com preliminary gs842z18/36ab-180/166/150/100 flow through mode read /write cycle timing *note: e = high (false) if e 1 = 1 or e 2 = 0 or e 3 = 1 ck cke e * adv tkh w tkl tkc b n a 0 ?an th ts a7 dq 12 3 4 56 7 8 9 10 command write d(a1) write d(a2) burst write d(a2+1) read q(a3) read q(a4) burst read q(a4+1) write d(a5) read q(a6) write d(a7) deselect don?t care undefined th ts th ts th ts th ts th ts a1 a2 a3 a4 a5 a6 d(a1) d(a2) q(a3) q q(a6) th ts d d(a5) tlz tkq tkqx tolz tkqx thz toe q(a4) (a4+1) (a2+1) g tohz
rev: 1.02 11/2002 20/32 ? 2001, giga semiconductor, inc. specifications cited are subject to change without noti ce. for latest documentation see http://www.gsitechnology.com preliminary gs842z18/36ab-180/166/150/100 flow through mode no-op, st all and deselect timing *note: e = high (false) if e 1 = 1 or e 2 = 0 or e 3 = 1 ck cke e * adv w bn a 0 ?an q(a5) dq 12 3 4 56 7 8 9 10 command write d(a1) read q(a2) stall read q(a3) write d(a4) stall nop read q(a5) continue don?t care undefined d(a4) thz tkqx deselect deselect d(a1) q(a2) q(a3) a1 a5 a2 a3 a4 th ts th ts th ts
rev: 1.02 11/2002 21/32 ? 2001, giga semiconductor, inc. specifications cited are subject to change without noti ce. for latest documentation see http://www.gsitechnology.com preliminary gs842z18/36ab-180/166/150/100 jtag port operation overview the jtag port on this ram operates in a manner that is co mpliant with ieee standard 1149.1-1990, a serial boundary scan interfa ce standard (commonly referred to as jtag). the jtag port input interface levels scale with v dd . the jtag output drivers are powered by v ddq . disabling the jtag port it is possible to use this device without utilizing the jtag port. the port is reset at power-up and will remain i nactive unles s clocked. tck, tdi, and tms are designed with internal pull-up circ uits.to assure normal operation of the ram with the jtag port unused, tck, tdi, and tms may be left floating or tied to either v dd or v ss . tdo should be left unconnected. jtag port registers overview the various jtag registers, refered to as test access port or tap registers, are selected (one at a time) via the sequences of 1 s and 0s applied to tms as tck is strobed. each of the tap registers is a serial shift register that captures seri al input data on the rising ed ge of tck and pushes serial data out on the next falling edge of tck. when a regist er is selected, it is placed between the tdi and tdo pins. instruction register the instruction register holds the instruct ions that are executed by the tap controlle r when it is moved into the run, test/idl e, or the various data register states. instructions are 3 bits long. the instruction register can be loade d when it is placed between the tdi and tdo pins. the instruction register is automatically prel oaded with the idcode instruction at power- up or whenever the controller is placed in test-logic-reset state. bypass register the bypass register is a single bit register that can be placed between tdi and td o. it allows serial test data to be passed th rough the ram?s jtag port to another device in the sc an chain with as little delay as possible. jtag pin descriptions pin pin name i/o description tck test clock in clocks all tap events. all i nputs are captured on the rising edge of tck and all outputs propagate from the falling edge of tck. tms test mode select in the tms input is sampled on the rising edge of tck. this is the command input for the tap controller state machine. an undriven tms input wi ll produce the same result as a logic one input level. tdi test data in in the tdi input is sampled on the rising edge of tck. this is the input side of the serial registers placed between tdi and tdo. the register pl aced between tdi and tdo is determined by the state of the tap controller state machine and the instruction that is currently loaded in the tap instruction register (refer to the tap controll er state diagram). an undriven tdi pin will produce the same result as a logic one input level. tdo test data out out output that is active depending on the state of the tap state machine. output changes in response to the falling edge of tck. this is the out put side of the serial registers placed between tdi and tdo. note: this device does not have a trst (tap rese t) pin. trst is optional in ieee 1149.1. the test-logic-reset state is entered while tms is held high for five rising edges of tck. the tap cont roller is also reset aut omaticly at power-up.
rev: 1.02 11/2002 22/32 ? 2001, giga semiconductor, inc. specifications cited are subject to change without noti ce. for latest documentation see http://www.gsitechnology.com preliminary gs842z18/36ab-180/166/150/100 boundary scan register the boundary scan register is a collection of flip flops that c an be preset by the logic level found on the ram?s input or i/o pins. the flip flops are then daisy chained together so the levels found can be shifted seria lly out of the jtag port?s tdo pin. the boundary scan regi ster also includes a number of place holder flip flops (always set to a logic 1). the relations hip between the device pins and the bits i n the boundary scan register is described in the scan order t able following. the boundary scan register, u nder the control of the tap controller, i s loaded with the contents of the rams i/o ring when the controller is in captur e-dr state and then is placed between the tdi and tdo pins when t he controller is moved to shift-dr state. sample-z, sample/preload and extest in structions can be used to activate the boundary scan register. jtag tap block diagram identification (id) register the id register is a 32-bit r egister that is loaded with a device and vendor s pecific 32-bit code when the controller is put in capture-dr state with the idcode command loaded in the instruction register. the code is loaded from a 32-bit on-chip ro m. it describes various attri butes of the ram as indicated below. the register is t hen placed between the tdi and tdo pins when the controller is moved into shift-dr sta te. bit 0 in the register is the lsb and the first to reach tdo when shifting begins. id register contents die revision code not used i/o configuration gsi technology jedec vendor id code presence register bit # 31302928272625242322212019181716151413121110987654321 0 x36 xxxx0000000000001000000110110011 x18 xxxx0000000000001010000110110011 instruction register id code register boundary scan register 0 1 2 0 1 2 31 30 29 0 1 2 n 0 bypass register tdi tdo tms tck test access port (tap) controller
rev: 1.02 11/2002 23/32 ? 2001, giga semiconductor, inc. specifications cited are subject to change without noti ce. for latest documentation see http://www.gsitechnology.com preliminary gs842z18/36ab-180/166/150/100 tap controller instruction set overview there are two classes of instructions defined in the standard 1149.1-1990; the standard (public) instructions, and device speci fic (private) instructions. some public instructions are mandatory for 1149.1 compliance. optional public instructions must be implemented in prescribed ways. the tap on this device may be used to monitor all input and i/o pads, and can be used to load address, data or control si gnals into the ram or to preload the i/o buffers. when the tap controller is placed in capture-ir state the two l east significant bits of the in struction register are loaded wit h 01. when the controller is moved to the shift-ir state the instruction regi ster is placed between tdi and tdo. in this state the desired ins truction is serially loaded through the tdi input (while the previous contents are shifted out at tdo) . for all instructions, the tap executes newly loaded instructions only when the controller is moved to update- ir state. the tap instruction set for this device is listed in the following table. jtag tap controller state diagram instruction descriptions bypass when the bypass instruction is loaded in the instruction register the bypass register is placed between tdi and tdo. this occur s when the tap controller is moved to the shift-dr state. this allo ws the board level scan path to be shortened to facilitate testing of other devices in the scan path. select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir test logic reset run test idle 0 0 1 0 1 1 0 0 1 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 10 0 0 1 11 1
rev: 1.02 11/2002 24/32 ? 2001, giga semiconductor, inc. specifications cited are subject to change without noti ce. for latest documentation see http://www.gsitechnology.com preliminary gs842z18/36ab-180/166/150/100 sample/preload sample/preload is a standard 1149.1 mandatory public instruction. when the sample / preload instruction is loaded in the instru c- tion register, moving the tap controller into the capture-dr state loads the data in the rams input and i/o buffers into the bo undary scan register. boundary scan register locations are not associated with an input or i/o pin, and are loaded with the default state i dentified in the boundary scan chain table at the end of this section of the dat asheet. because the ram clock is independent from the tap clock (tck) it is possible for the tap to attempt to capture the i/o ring conten ts while the input buffers are in transition (i.e. in a metast able state). although allowing the tap to sample metastable inputs will not harm the device, repeatable results cannot be expected. ram input signals must be stabilized for long enough to meet the taps input data capture set- up plus hold time (tts plus tth). the rams clock inputs need not be paused for any other tap operation except capturing the i/o ring contents into the boundary scan r egister. moving the controlle r to shift- dr state then places the boundary scan register between t he tdi and tdo pins. extest extest is an ieee 1149.1 mandatory public instruction. it is to be executed whenever the instruct ion register is loaded with al l logic 0s. the extest command does not block or override the ram?s input pins; ther efore, the ram?s internal state is still determined by its input pins. typically, the boundary scan register is loaded with the desired pa ttern of data with the sample/preload command. then the exte st command is used to output the boundary scan register?s contents, in parallel, on the ram?s dat a output drivers on the falling e dge of tck when the controller is in the update-ir state. alternately, the boundary scan register may be loaded in parallel using the extest command. when the extest instruction is sele cted, the sate of all the ram?s input and i/o pins, as well as the defaul t values at scan register lo cations not associated with a pi n, are trans- ferred in parallel into the boundary scan register on the rising edge of tck in the capture-dr state, the ram?s output pins dri ve out the value of the boundary scan register location wi th which each output pin is associated. idcode the idcode instruction causes the id rom to be loaded into the id register when the controller is in capture-dr mode and places the id register between the tdi and tdo pins in sh ift-dr mode. the idcode instruction is t he default instruction loaded in at power up and any time the controller is placed in the test-logic-reset state. sample-z if the sample-z instruction is loaded in the instruction register , all ram outputs are forced to an inactive drive state (high- z) and the bound- ary scan register is connected between tdi and tdo when the tap controller is moved to the shift-dr state. rfu these instructions are reserved for future use. in this device they replicate the bypass instruction.
rev: 1.02 11/2002 25/32 ? 2001, giga semiconductor, inc. specifications cited are subject to change without noti ce. for latest documentation see http://www.gsitechnology.com preliminary gs842z18/36ab-180/166/150/100 jtag tap instruction set summary instruction code description notes extest 000 places the boundary scan register between tdi and tdo. 1 idcode 001 preloads id register and pl aces it between tdi and tdo. 1, 2 sample-z 010 captures i/o ring contents. places the b oundary scan register between tdi and tdo. forces all ram output drivers to high-z. 1 rfu 011 do not use this instruction; reserved for future use. replicates bypass instruction. plac es bypass register between tdi and tdo. 1 sample/preload 100 captures i/o ring contents. places the boundary scan register between tdi and tdo. 1 gsi 101 gsi private instruction. 1 rfu 110 do not use this instruction; reserved for future use. replicates bypass instruction. plac es bypass register between tdi and tdo. 1 bypass 111 places bypass register between tdi and tdo. 1 notes: 1. instruction codes expressed in binary, msb on left, lsb on right. 2. default instruction automatically loaded at power-up and in test-logic-reset state.
rev: 1.02 11/2002 26/32 ? 2001, giga semiconductor, inc. specifications cited are subject to change without noti ce. for latest documentation see http://www.gsitechnology.com preliminary gs842z18/36ab-180/166/150/100 jtag port recommended operating conditions and dc characteristics parameter symbol min. max. unit notes 3.3 v test port input high voltage v ihj3 2.0 v dd3 +0.3 v1 3.3 v test port input low voltage v ilj3 ? 0.3 0.8 v1 2.5 v test port input high voltage v ihj2 0.6 * v dd2 v dd2 +0.3 v1 2.5 v test port input low voltage v ilj2 ? 0.3 0.3 * v dd2 v1 tms, tck and tdi input leakage current i inhj ? 300 1 ua 2 tms, tck and tdi input leakage current i inlj ? 1 100 ua 3 tdo output leakage current i olj ? 11ua4 test port output high voltage v ohj 1.7 ? v5, 6 test port output low voltage v olj ? 0.4 v 5, 7 test port output cmos high v ohjc v ddq ? 100 mv ? v5, 8 test port output cmos low v oljc ? 100 mv v 5, 9 notes: 1. input under/overshoot voltage must be ? 2 v > vi < v ddn +2 v not to exceed 4.6 v maximum, with a pulse width not to exceed 20% ttkc. 2. v ilj v in v ddn 3. 0 v v in v iljn 4. output disable, v out = 0 to v ddn 5. the tdo output driver is served by the v ddq supply. 6. i ohj = ? 4 ma 7. i olj = + 4 ma 8. i ohjc = ?100 ua 9. i ohjc = +100 ua
rev: 1.02 11/2002 27/32 ? 2001, giga semiconductor, inc. specifications cited are subject to change without noti ce. for latest documentation see http://www.gsitechnology.com preliminary gs842z18/36ab-180/166/150/100 jtag port timing diagram notes: 1. include scope and jig capacitance. 2. test conditions as as shown unless otherwise noted. jtag port ac test conditions parameter conditions input high level 2.3 v input low level 0.2 v input slew rate 1 v/ns input reference level 1.25 v output reference level 1.25 v dq v t = 1.25 v 50 ? 30pf * jtag port ac test load * distributed test jig capacitance ttkq tts tth ttkh ttkl tck tms tdi tdo ttkc
rev: 1.02 11/2002 28/32 ? 2001, giga semiconductor, inc. specifications cited are subject to change without noti ce. for latest documentation see http://www.gsitechnology.com preliminary gs842z18/36ab-180/166/150/100 jtag port ac electrical characteristics parameter symbol min max unit tck cycle time ttkc 50 ? ns tck low to tdo valid ttkq ? 20 ns tck high pulse width ttkh 20 ? ns tck low pulse width ttkl 20 ? ns tdi & tms set up time tts 10 ? ns tdi & tms hold time tth 10 ? ns
rev: 1.02 11/2002 29/32 ? 2001, giga semiconductor, inc. specifications cited are subject to change without noti ce. for latest documentation see http://www.gsitechnology.com preliminary gs842z18/36ab-180/166/150/100 output driver characteristics tbd
rev: 1.02 11/2002 30/32 ? 2001, giga semiconductor, inc. specifications cited are subject to change without noti ce. for latest documentation see http://www.gsitechnology.com preliminary gs842z18/36ab-180/166/150/100 package dimensions?119-bump bga bpr 1999.05.18 n p a b pin 1 corner k e f ct a b c d e f g h j k l m n p r t u g s d 1 2 3 4 5 6 7 package dimensions?119-pin bga unit: mm symbol description min. nom. max a width 13.8 14.0 14.2 b length 21.8 22.0 22.2 c package height (including ball) - 2.40 d ball size 0.60 0.75 0.90 e ball height 0.50 0.60 0.70 f package height (excluding balls) 1.46 1.70 g width between balls 1.27 k package height above board 0.80 0.90 1.00 n cut-out package width 12.00 p foot length 19.50 r width of package between balls 7.62 s length of package between balls 20.32 t variance of ball height 0.15 bottom view r top view side view
rev: 1.02 11/2002 31/32 ? 2001, giga semiconductor, inc. specifications cited are subject to change without noti ce. for latest documentation see http://www.gsitechnology.com preliminary gs842z18/36ab-180/166/150/100 ordering information?gsi nbt synchronous sram org part number 1 type package speed 2 (mhz/ns) t a 3 status 256k x 18 GS842Z18AB-180 nbt pipeline/flow through bga 180/8 c 256k x 18 gs842z18ab-166 nbt pipeline/flow through bga 166/8.5 c 256k x 18 gs842z18ab-150 nbt pipeline/flow through bga 150/10 c 256k x 18 gs842z18ab-100 nbt pipeline/flow through bga 100/12 c 128k x 36 gs842z36ab-180 nbt pipeline/flow through bga 180/8 c 128k x 36 gs842z36ab-166 nbt pipeline/flow through bga 166/8.5 c 128k x 36 gs842z36ab-150 nbt pipeline/flow through bga 150/10 c 128k x 36 gs842z36ab-100 nbt pipeline/flow through bga 100/12 c 256k x 18 GS842Z18AB-180i nbt pipeline/flow through bga 180/8 i 256k x 18 gs842z18ab-166i nbt pipeline/flow through bga 166/8.5 i 256k x 18 gs842z18ab-150i nbt pipeline/flow through bga 150/10 i 256k x 18 gs842z18ab-100i nbt pipeline/flow through bga 100/12 i 128k x 36 gs842z36ab-180i nbt pipeline/flow through bga 180/8 i 128k x 36 gs842z36ab-166i nbt pipeline/flow through bga 166/8.5 i 128k x 36 gs842z36ab-150i nbt pipeline/flow through bga 150/10 i 128k x 36 gs842z36ab-100i nbt pipeline/flow through bga 100/12 i notes: 1. customers requiring delivery in tape and r eel should add the character ?t? to the end of the part number. example: gs842z36ab -100it. 2. the speed column indicates the cycle frequenc y (mhz) of the device in pipeline mode and the latency (ns) in flow through mod e. each device is pipeline/flow through mode-selectable by the user. 3. t a = c = commercial temperature range. t a = i = industrial temperature range. 4. gsi offers other versions this type of device in many different configurations and with a variety of different features, onl y some of which are covered in this data sheet. see t he gsi technology web site (www.gsitechnology.com ) for a complete listing of current offerings
rev: 1.02 11/2002 32/32 ? 2001, giga semiconductor, inc. specifications cited are subject to change without noti ce. for latest documentation see http://www.gsitechnology.com preliminary gs842z18/36ab-180/166/150/100 4mb synchronous nbt dat asheet revision history ds/daterev. code: old; new types of changes format or content page /revisions/reason 842z18a_r1 ? creation of new datasheet 842z18a_r1; 842z18a_r1_01 content ? updated power numbers in table on page 1 and operating currents table ? updated pinout for x18 ? updated pin description table ? removed bytesafe references ? changed dp and qe to nc ? delete pe from entire document (changed to nc) 842z18a_r1_01; 842z18a_r1_02 content ? removed 200 mhz speed bin ? removed pin locations from pin description table

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